In the integrated MOS transistors, the noise factor has long been subject to limited research due to the fact that these components were ? and still are ? used primarily in digital applications, hence with large signals, where the fundamental requirements of the component are speed and low power consumption. However, the refinement of the technologies has led to ever smaller components and it is enabling to integrate on the same chip complex systems, often including analog and digital parts, stimulating the in-depth study of the performance of the MOSs regarding noise and the interest in optimizing technological processes in this regard. It should also be noted that, even in purely digital applications, the intrinsic noise of the component is a factor to be taken into account; very often, in fact, the component noise, whether it is a transistor or a simple metal strip, is deeply tied to its reliability, as excessive noise is often due to imperfections and defects in its microstructure. The noise characterization can therefore also be interesting as it would allow a component reliability estimation without having to use accelerated stress methods. The case of transistor-metal-insulating-semiconductor structure is an emblematic case. Such devices are known to be noisy than the junctions FET precisely because the conduction occurs near the semiconductor-insulator interface that has more crystal defects than the bulk of the semiconductor itself. At the same time, one of the causes of death of transistors is the breakup of the oxide, or the trapping by it of a spurious charge that makes the device unusable; both phenomena are favored by a worse interface. Here, at least qualitatively, the bond between the noise and reliability of a MOS transistor. The first part of the thesis is centered on flicker noise measurement in MOS transistors, oriented toward the search for a noise quality parameter for MOS transistors, which is to be used in comparing different technological processes, optimizing them in order to obtain a better semiconductor-isolating interface. The second part is dedicated to the study of gate noise in MOS and JFET transistors, and illustrates the methods used to investigate this noise and the results obtained.
Universidad de Padua. Padua (Italia)
13 September 1993
R. Giannetti (1993), Misura e modelli di rumore in transistores MOS. Universidad de Padua. Padua (Italy).